The Instruction Set Architecture (ISA) of a processor defines its operational characteristics. Given the development investment in tools and application code for the processor, the ISA typically represents a fixed quantity with minimal room for growth. It is possible to develop supersets of an instruction set architecture, but even this is many times difficult given that the overall fixed core ISA is usually defined without scalability, i.e., planned growth, in mind. In addition, it is a difficult problem to develop a single ISA for a family of array processors in order to amortize development expenses across a family of products, encompassing a range of 16-bit, 32-bit, and larger instruction set formats. Thus, it has been recognized that it will be highly advantageous to have a hierarchical instruction set as discussed further below.